1. Field of the Invention
The present invention relates to a flip chip package module and, more particularly, to a flip chip package module with enhanced thermal dissipation and a method of forming the same.
2. Discussion of the Background
Flip chip package is an advanced packaging technique for connecting a semiconductor chip to a substrate. During the packaging process, the semiconductor chip is turned upside down to connect to the metal pads and hence the metal conductive wires of the substrate.
Please refer first to FIG. 1 for the cross-sectional diagram of a flip chip package module in accordance with the prior art. The flip chip package module generally consists of a substrate 10, a semiconductor chip 12, a plurality of bumps 14, an underfill layer 16, and a plurality of solder balls 18.
The substrate 10 is an insulating material with two sides that have respectively a first metal interconnect layer 101 and a second metal interconnect layer 102. The first and the second metal interconnect layers 101 and 102 have respectively a plurality of metal conductive wires locatedtherein, and are electrically connected by means of a plurality of vias 11. The circuit side (positive side) of the semiconductor chip 12 has a plurality of die pads. Under bump metallurgy (UBM) has to be formed on the die pad surface before forming the bumps 14 thereon. The semiconductor chip 12 is bonded by soldering to the first metal interconnect layer 101 of the substrate 10 through the bumps 14 on its surface. Then an underfill layer 16 is formed between the semiconductor chip 12 and the substrate 10 to increase the mechanical bonding strength. In addition, every metal conductive wire on the second metal interconnect layer 102 connects to a solder pad for the purpose of soldering a solder ball 18.
However, the prior art has the following disadvantage:
1. UBM (Under Bump Metallurgy) must be formed on the die pads before applying the bumps for bonding the semiconductor chip onto the first metal interconnect layer of the substrate. The processes of making UBM and the bumps are costly.
2. The substrate in the prior art usually contains muitiple layers (four or six metal interconnect layers). Therefore, the manufacturing process of the conventional substrate is very costly.
3. The probe card for testing electricity of the semocinductor chip adopted for the semocinductor chip with bumps is more expensive.
4. When applying the prior art for packaging the flip chip of multi-chip module (MCM) that has different chip thickness, it is difficult to bond a single heat sink to the MCM package die surfaces, due to the incoplanarity of the die surfaces. As a result, total heat dissipation suffers.
One object of the present invention is to provide a flip chip package module.
Another object of the present invention relates to a method for forming the flip chip package module.
The flip chip package module disclosed according to the present invention comprises a semicomductor chip, a heat sink plate, a dielectric layer and a metal interconnect layer. The semicomductor chip has a positive side with a plurality of die pads located thereon and a back side directly bonded to the heat sink plate. The dielectric layer is formed on the inner surface of the heat sink plate by depositing dielelctric material(s) and the semicomductor chip is encased therein in the mean time. The surface of the dielectric layer has a metal interconnect layer which consists of a plurality of metal conductive wires. Every metal conductive wire connects electrically to one of the die pads of the semiconductor chip through a via. Furthermore, every metal conductive wire connects to a pad for soldering solder balls or enabling a test probe to perform electric test for the semiconductor chip.
The present invention also discloses a method of forming the flip chip package module. The method comprises the following steps. First, a heat sink plate is provided. Then bond the back side of a semiconductor chip to the heat sink plate. Thereafter, deposit a dielectric layer on the inner surface of the heat sink plate and encase the semiconductor chip therein. Then grind the dielectric layer through a CMP (Chemical Mechanical Planarization) process.
After the planarization process, form a plurality of via holes on the surface of the dielectric layer by laser drilling or dry etching process. Each via hole connect to a die pad located on the positive side of the semiconductor chip. Then form a metal interconnect layer on the surface of the dielectric layer by metal deposition and fill the via holes during the same process to form a plurality of vias. Finally form a plurality of metal conductive wires and pads by performing a photo lithographic process and an etching process.